==== Cvičení 2 ====
neručím za správnost, pokud mě doplní, kdo si je jistější budu rád:
=== 1. ===
<code verilog>
module KonecnyAutomat(input x, clk, reset,
                      output [2:0] y);
	 
	reg [2:0] state, nextstate;
	 
	parameter S0 = 3'b000;
	parameter S1 = 3'b001;
	parameter S2 = 3'b010;
	parameter S3 = 3'b011;
	parameter S4 = 3'b100;
	 
	always @ (posedge clk, posedge reset)
		if (reset) state = S0;
		else state = nextstate;
	
	always @(*) 
		case (state)
			S0: if (x) nextstate = S4;
			    else nextstate = S1;
			S1: if (x) nextstate = S0;
			    else nextstate = S2;
			S2: if (x) nextstate = S1;
			    else nextstate = S3;
			S3: if (x) nextstate = S2;
			    else nextstate = S4;
			S4: if (x) nextstate = S3;
			    else nextstate = S0;
			default: nextstate = S0;
		endcase
	
	assign y = state;

endmodule
</code>

=== 4. ===

<code verilog>
module mux2x1(in0, in1, select, out);
    input [31:0] in0;
    input [31:0] in1;
    input select;
    output [31:0] out;	 
	 assign out = select ? in1 : in0;
endmodule
</code>
<code verilog>
module mux3x1(in0, in1, in2, select, out);
    input [31:0] in0;
    input [31:0] in1;
    input [31:0] in2;
    input [1:0] select;
    output [31:0] out;	 
	 case (select)
		2'b00: assign out = in0;
		2'b01: assign out = in1;
		2'b10: assign out = in2;
		default: assign out = in0;
	 endcase
endmodule
</code>
<code verilog>
module sumator(a, b, suma);
    input [31:0] a;
    input [31:0] b;
    output [31:0] suma;	 
	 assign suma = a+b;
endmodule
</code>
<code verilog>
module mul4(in, out);
    input [31:0] in;
    output [31:0] out;
	assign out = 4*in;
endmodule
</code>
<code verilog>
module compare(a, b, out);
    input [31:0] a;
    input [31:0] b;
    output out;	 
	 assign out = (a == b) ? 1 : 0;
endmodule
</code>
<code verilog>
module extend(
    input [15:0] in,
    output [31:0] out
    );
	assign out = { {16{in[15]}}, in };
endmodule
</code>
<code verilog>
module registr(
    input [31:0] in,
    input enable,
    input reset,
    input clk,
    output [31:0] out
    );
	 reg [31:0] data = 0;	 
	 always @ (posedge clk, posedge reset)
		if (reset) data = 0;
		else if (enable) data = in;		
	 assign out = data;
endmodule
</code>
<code verilog>
module pole(
    input [4:0] addr0,
    input [4:0] addr1,
    input [4:0] addr2,
    input [31:0] in,
    input enable,
    input clk,
    output [31:0] out0,
    output [31:0] out1
    );	 
	 reg[31:0] regs[0:31];
	 reg [5:0] i;
	 initial begin
		for (i=0;i<=31;i=i+1) regs[i] = 0; //initialize registers--just so they aren?t cares
	 end	 
	 always @ (posedge clk)
		if (enable && addr2 > 0) regs[addr2] = in;	 
	 assign out0 = regs[addr0];
	 assign out1 = regs[addr1];
endmodule
</code>
<code verilog>
module alu(
    input [31:0] srcA,
    input [31:0] srcB,
    input [2:0] ALUcontrol,
    output [31:0] ALUout,
    output zero
    );	 
	 reg[31:0] out=0;	 
	 always @(*)
	 case (ALUcontrol)
		3'b010: out = srcA + srcB;
		3'b110: out = srcA - srcB;
		3'b000: out = srcA & srcB;
		3'b001: out = srcA | srcB;
		3'b011: out = srcA ^ srcB;
		3'b111: out = (srcA < srcB) ? 1 : 0;
		default: out = 0;
	 endcase
	 assign ALUout = out;
	 assign zero = (out==0) ? 1 : 0;
endmodule
</code>

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