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courses:a4m36pap:cviceni3 [2010/10/13 23:54] redtop created |
courses:a4m36pap:cviceni3 [2025/01/03 18:29] (aktuální) |
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|---|---|---|---|
| Řádek 1: | Řádek 1: | ||
| - | ===== Cvičení 2 ===== | + | ===== Cvičení 3 ===== |
| ==== 1. ==== | ==== 1. ==== | ||
| - | <code> | + | <code verilog> |
| module maindec(Opcode, RegWrite, RegDst, ALUSrc, ALUOp, Branch, MemWrite, MemToReg); | module maindec(Opcode, RegWrite, RegDst, ALUSrc, ALUOp, Branch, MemWrite, MemToReg); | ||
| input [5:0] Opcode; | input [5:0] Opcode; | ||
| Řádek 15: | Řádek 15: | ||
| always @(*) | always @(*) | ||
| case(Opcode) | case(Opcode) | ||
| - | 000000: out= 8'b11010000; | + | 6'b000000: out= 8'b11010000; |
| - | 100011: out= 8'b10100001; | + | 6'b100011: out= 8'b10100001; |
| - | 101011: out= 8'b0x10001x; | + | 6'b101011: out= 8'b00100010; |
| - | 000100: out= 8'b0x00110x; | + | 6'b000100: out= 8'b00001100; |
| - | 001000: out= 8'b10100000; | + | 6'b001000: out= 8'b10100000; |
| endcase | endcase | ||
| assign {RegWrite, RegDst, ALUSrc, ALUOp, Branch, MemWrite, MemToReg} = out; | assign {RegWrite, RegDst, ALUSrc, ALUOp, Branch, MemWrite, MemToReg} = out; | ||
| endmodule | endmodule | ||
| </code> | </code> | ||
| - | <code> | + | <code verilog> |
| module aludec(ALUOp, Funct, ALUControl); | module aludec(ALUOp, Funct, ALUControl); | ||
| input [1:0] ALUOp; | input [1:0] ALUOp; | ||
| Řádek 31: | Řádek 31: | ||
| always @(*) | always @(*) | ||
| case(ALUOp) | case(ALUOp) | ||
| - | 00: ALUControl = 3'b010; | + | 2'b00: ALUControl = 3'b010; |
| - | 01: ALUControl = 3'b110; | + | 2'b01: ALUControl = 3'b110; |
| default: | default: | ||
| case(Funct) | case(Funct) | ||
| - | 100000: ALUControl = 3'b010; | + | 6'b100000: ALUControl = 3'b010; |
| - | 100010: ALUControl = 3'b110; | + | 6'b100010: ALUControl = 3'b110; |
| - | 100100: ALUControl = 3'b000; | + | 6'b100100: ALUControl = 3'b000; |
| - | 100101: ALUControl = 3'b001; | + | 6'b100101: ALUControl = 3'b001; |
| - | 101010: ALUControl = 3'b111; | + | 6'b101010: ALUControl = 3'b111; |
| endcase | endcase | ||
| endcase | endcase | ||
| endmodule | endmodule | ||
| </code> | </code> | ||
| - | <code> | + | <code verilog> |
| module controlunit(Opcode, Funct, Zero, RegWrite, RegDst, ALUSrc, PCSrc, MemWrite, MemToReg, ALUControl); | module controlunit(Opcode, Funct, Zero, RegWrite, RegDst, ALUSrc, PCSrc, MemWrite, MemToReg, ALUControl); | ||
| input [5:0] Opcode; | input [5:0] Opcode; | ||
| Řádek 67: | Řádek 67: | ||
| ==== 2. ==== | ==== 2. ==== | ||
| + | <code> | ||
| + | addi $s0, $0, 0x0010 | ||
| + | lw $s1, 0($s0) //load a | ||
| + | lw $s2, 4($s0) //load b | ||
| + | lw $s3, 8($s0) //load c | ||
| + | |||
| + | slt $t0, $s2, $s1 //if(b<a)t0=1 else t0=0 | ||
| + | beq $t0, $0, if //if(t0=0) if vetev | ||
| + | sub $s1, $s1, $s2 //a=a-b | ||
| + | beq $0, $0, L2 //jump | ||
| + | if: | ||
| + | addi $t1, $0, 0 //i=0 | ||
| + | while: | ||
| + | beq $t1, $s3, done //if(i=c) konec cyklu | ||
| + | add $s1, $s1, $t1 //a+=i | ||
| + | addi $t1, $t1, 1 //i++ | ||
| + | beq $0, $0, while //jump | ||
| + | done: | ||
| + | L2: | ||
| + | | ||
| + | sw $s1, 0($s0) //store a | ||
| + | </code> | ||
| ~~DISCUSSION~~ | ~~DISCUSSION~~ | ||
