module maindec(Opcode, RegWrite, RegDst, ALUSrc, ALUOp, Branch, MemWrite, MemToReg);
    input [5:0] Opcode;
    output RegWrite;
    output RegDst;
    output ALUSrc;
    output [1:0] ALUOp;
    output Branch;
    output MemWrite;
    output MemToReg;
	 reg[7:0] out=0;
	 always @(*)
	 case(Opcode)
		000000: out= 8'b11010000;
		100011: out= 8'b10100001;
		101011: out= 8'b00100010;
		000100: out= 8'b00001100;
		001000: out= 8'b10100000;
	 endcase
	 assign {RegWrite, RegDst, ALUSrc, ALUOp, Branch, MemWrite, MemToReg} = out;
endmodule

module aludec(ALUOp, Funct, ALUControl);
    input [1:0] ALUOp;
    input [5:0] Funct;
    output reg [2:0] ALUControl;
	 always @(*)
	 case(ALUOp)
		00: ALUControl = 3'b010;
		01: ALUControl = 3'b110;
		default:
			case(Funct)
				100000: ALUControl = 3'b010;
				100010: ALUControl = 3'b110;
				100100: ALUControl = 3'b000;
				100101: ALUControl = 3'b001;
				101010: ALUControl = 3'b111;
			endcase
	 endcase
endmodule

module controlunit(Opcode, Funct, Zero, RegWrite, RegDst, ALUSrc, PCSrc, MemWrite, MemToReg, ALUControl);
    input [5:0] Opcode;
    input [5:0] Funct;
    input Zero;
    output RegWrite;
    output RegDst;
    output ALUSrc;
    output PCSrc;
    output MemWrite;
    output MemToReg;
    output [2:0] ALUControl;	 
	 wire [1:0] ALUOp;
	 wire Branch;	 
	 maindec mdec(Opcode, RegWrite, RegDst, ALUSrc, ALUOp, Branch, MemWrite, MemToReg);
	 aludec adec(ALUOp, Funct, ALUControl);	 
	 assign PCSrc = Zero & Branch;
endmodule