module maindec(Opcode, RegWrite, RegDst, ALUSrc, ALUOp, Branch, MemWrite, MemToReg);
    input [5:0] Opcode;
    output RegWrite;
    output RegDst;
    output ALUSrc;
    output [1:0] ALUOp;
    output Branch;
    output MemWrite;
    output MemToReg;
	 reg[7:0] out=0;
	 always @(*)
	 case(Opcode)
		000000: out= 8'b11010000;
		100011: out= 8'b10100001;
		101011: out= 8'b00100010;
		000100: out= 8'b00001100;
		001000: out= 8'b10100000;
	 endcase
	 assign {RegWrite, RegDst, ALUSrc, ALUOp, Branch, MemWrite, MemToReg} = out;
endmodule

module aludec(ALUOp, Funct, ALUControl);
    input [1:0] ALUOp;
    input [5:0] Funct;
    output reg [2:0] ALUControl;
	 always @(*)
	 case(ALUOp)
		00: ALUControl = 3'b010;
		01: ALUControl = 3'b110;
		default:
			case(Funct)
				100000: ALUControl = 3'b010;
				100010: ALUControl = 3'b110;
				100100: ALUControl = 3'b000;
				100101: ALUControl = 3'b001;
				101010: ALUControl = 3'b111;
			endcase
	 endcase
endmodule

module controlunit(Opcode, Funct, Zero, RegWrite, RegDst, ALUSrc, PCSrc, MemWrite, MemToReg, ALUControl);
    input [5:0] Opcode;
    input [5:0] Funct;
    input Zero;
    output RegWrite;
    output RegDst;
    output ALUSrc;
    output PCSrc;
    output MemWrite;
    output MemToReg;
    output [2:0] ALUControl;	 
	 wire [1:0] ALUOp;
	 wire Branch;	 
	 maindec mdec(Opcode, RegWrite, RegDst, ALUSrc, ALUOp, Branch, MemWrite, MemToReg);
	 aludec adec(ALUOp, Funct, ALUControl);	 
	 assign PCSrc = Zero & Branch;
endmodule

addi $s0, $0, 0x0010
lw $s1, 0($s0)           //load a
lw $s2, 4($s0)           //load b
lw $s3, 8($s0)           //load c

slt $t0, $s2, $s1        //if(b<a)t0=1 else t0=0
beq $t0, $0, if          //if(t0=0) if vetev
  sub $s1, $s1, $s2      //a=a-b
  beq $0, $0, L2       //jump
if:
  addi $t1, $0, 0          //i=0
  while:
    beq $t1, $s3, done     //if(i=c) konec cyklu
    add $s1, $s1, $t1      //a+=i
    addi $t1, $t1, 1       //i++
    beq $0, $0, while    //jump
  done:
L2:
  
sw $s1, 0($s0)           //store a